Reference to Microfiche Appendix
Microfiche Appendix A of 2 sheets and 75 frames and microfiche Appendix B of 1 sheet and 58 frames are part of the present disclosure, and are incorporated herein by reference in their entirety.
Microfiche Appendices A and B include VERILOG code listings for generating the modules for a serial port for a host adapter integrated circuit and a slave serial port input-output integrated circuit respectively.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
The present invention is related generally to a serial port for an integrated circuit and in particular to a serial port for input and output of information to a circuit external to the integrated circuit using a single pin terminal of the integrated circuit.
2. Description of Related Art
As the number of functions performed by an integrated circuit, hereinafter IC, increases, typically the number of pins of the integrated circuit also increases. However, as a rule of thumb, a packaged integrated circuit with a large number of pins is more expensive to fabricate than an IC with relatively fewer pins. Also, a large number of pins adds to the cost of the board on which the IC is to be mounted. Packaged ICs with a large number of pins at the periphery cannot be used due to lack of real estate on the board. Packaged ICs with multiple rows of pins inside the periphery at the bottom of the package require additional layers in a board and increase complexity of interconnects on the board. The number of pins of an IC can also impose a limit on the number of functions that can be performed in the IC.
When an IC, such as host adapter 112A that interfaces an input-output bus, e.g. SCSI bus, to a host computer""s system bus, e.g. PCI bus, (FIG. 1A) is mounted on a plug-in board 110, the number of pins needed by host adapter 112A is not constrained in a majority of cases. Host adapter 112A (FIG. 1A) has a number of pins, such as pins 112-1, 112-2, . . . 112-N to support an adapter read-only-memory 111 for basic input-output software, hereinafter BIOS of host adapter 112A.
External logic (not shown) is needed by some host adapters to support adapter read-only-memory 111. For example, xe2x80x9c36C70 SCSI IC Technical Reference Manualxe2x80x9d by Future Domain Corporation, 2801 McGraw Avenue, Irvine, Calif. 92714, November 1993, discloses a host adapter in which xe2x80x9c[a] minimal amount of external glue logic is required to serialize the parallel ROM dataxe2x80x9d (page 3-1). During system start-up, the information from the adaptor read-only-memory can be copied into system memory 170 for quick access by host processor 161, sometimes referred to as microprocessor 161.
In contrast, when a host adapter 112B (FIG. 1B) is mounted on a mother board 60 of a personal computer, the number of pins of host adapter 112B can be limited to, for example, 100 pins due to less real estate available on mother board 160 as compared to plug-in board 110. Host adapter 112B eliminates the need for a connector that is otherwise necessary for a plug-in board. Host adapter 112B (FIG. 1B) does not have pins to access adapter read-only-memory 111, e.g. pins 112-1, 112-2, . . . 112-N of host adapter 112A (FIG. 1A). BIOS for host adapter 112B is loaded from processor read-only-memory 162 that also contains the system BIOS for microprocessor 161. Thus host adapter 112B is limited to performing only certain basic functions, such as data transfer between system bus 120 and input-output bus 140. Such a host adapter 112B cannot be used on plug-in board 110 e.g. if host adapter 112B does not support a read-only-memory.
A way is needed for a limited pin integrated circuit, such as host adapter 112B to use resources, such as a read-only-memory, without increasing the number of pins, so that the same host adapter 112B can be used on both a mother board and a plug-in board.
In accordance with the principles of this invention, a host adapter integrated circuit, henceforth xe2x80x9chost adapterxe2x80x9d, has a novel single pin serial port. The serial port uses a single bidirectional pin, for transfer of information from and to a circuit, such as a support circuit that is external to the host adapter. The support circuit contains resources that support certain functions that are not available in the host adapter.
The serial port allows various modules of host adapter, to communicate with the support circuit through the single serial port pin. The serial port also allows software on a host processor that is connected to the host adapter by a system bus to communicate with resources in the support circuit. The serial port has no other pins that are connected to the support circuit for information transfer, such as control pins for interrupt signals or other control signals for handshaking or a data clock pin. In one embodiment, the host adapter serial port and the support circuit are operated synchronous with each other by a common clock signal that originates from an oscillator. A sequencer module in the host adapter buffers the common clock signal and passes the buffered clock signal to various modules of the host adapter, including the serial port.
One embodiment of a host adapter includes a master serial port input-output circuit that receives various internal signals from various modules of the host adapter and drives one or more command signals active onto a serial port command bus that is connected to the serial port. In response to an active command signal, the serial port generates a command byte, formats the command byte into a packet and then transmits the packet on the serial port pin.
The serial port forms a packet from any bytes of information to be transferred, such as a command byte, an address byte or a data byte by adding a start bit before the byte, followed by a parity bit after the byte and a stop bit after the parity bit. After transmitting one or more packets to the support circuit, the serial port waits for an acknowledge packet from the support circuit.
In response to active command signals, the serial port generates and transmits a command packet optionally followed by one or more address packets and data packets serially on the serial port pin that is coupled to the support circuit. The serial port receives all responses from the support circuit on the same serial port pin.
In one embodiment, the serial port executes a command cycle to implement a serial port input-output protocol of a packet sequence specific to the command byte being transferred. For example, in response to a command signal to write one or two bits, such as a command to turn on and off (1) a light emitting diode, or (2) bus termination of the input-output bus or to reset a slave serial port input-output circuit included in the support circuit, the serial port executes a bit write command cycle in which the serial port includes the bits to be transmitted in the command byte, transmits a packet containing the command byte and waits for an acknowledge packet following transmission of the packet.
In response to a command signal to write a byte, for example to a predetermined register, in addition to transmitting a packet containing a command byte, the serial port also transmits a packet containing a data byte and then waits for the acknowledge packet.
In response to a command signal to write a byte to a specific address, for example to an electrically erasable programmable read only memory, the serial port transmits a packet containing command byte, followed by one or more packets containing the address bytes, e.g. two packets for a 16-bit address, followed by a packet containing the data byte and then waits for the acknowledge packet.
Similarly, in response to a command signal to read a byte, for example from a predetermined register, the serial port transmits a packet containing the command byte and then waits for an acknowledge packet that is followed by a packet containing the data in the register.
To read a four-byte word from an address in memory, such as a random-access-memory the serial port transmits a packet containing the command byte followed by two packets containing the address bytes and then waits for an acknowledge packet followed by four packets containing data bytes.
The support circuit determines the number of packets expected from the serial port of the host adapter from the contents of the packet containing the command byte. After receiving all expected packets, the support circuit starts transmission of an acknowledge packet and while transmitting the acknowledge packet, performs the operation indicated by the command byte. On completion of the operation, the support circuit terminates transmission of the acknowledge packet and depending on the operation transmits one or more data packets if necessary.
The use of such a serial port to off-load various functions of a host adapter to a support circuit is a significant improvement over prior art integrated circuits because the serial port reduces the number of pins of a host adapter. Such a host adapter can be used on a plug-in board with a support circuit, such as a slave serial port input-output circuit that provides various functions, such as support for an external read-only-memory. Instead of a slave serial port input-output circuit, a programmable logic circuit or a shift register can pass to the host adapter, for example, a device identification byte and byte of status of various resources accessible through the serial port. The same host adapter can also be used on a personal computer mother board to provide data transfer functions, without a support circuit.
In response to an active bit in a serial port control register, the serial port operates in a test mode in which the serial port passes an internal signal of the host adapter to the serial port pin. The serial port exits the test mode only when reset.
In one embodiment, in the absence of a support circuit, the serial port pin that is normally used for information transfer is used by the host adapter for a default internal signal, such as turning power for bus termination on and off, which further reduces the total number of pins. Such a host adapter results in lower cost due to a smaller number of pins, smaller die size and volume production for use on a mother board as well as a plug-in board. Such a host adapter also takes less space on a mother board and so reduces the overall system cost for supporting data transfer between a system bus and an input-output bus.
The use of such a predetermined protocol in which one integrated circuit always waits for another integrated circuit eliminates possibility of contention for serial port input-output line avoids collision of packets and so eliminates need for control lines, in addition to serial port input-output line between a serial port of a host adapter and a support circuit.